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Feature #218

Von Maximilian Seesslen vor mehr als 2 Jahren aktualisiert

Clean up all the timing calculation garbage.
The values should be determined only by the periphery clock (MCU) Frequency and bus Speed.

This has to be done for FDCAN and classic CAN.

Check if CFdCan and CCan can be merged. Filter is a little bit different. There are already different HAL-implementations for Classic-CAN.



Fuer 13/2: prescaler=Clock/speed/16; (Clock/speed)%16 muss 0 sein
48Mhz, 125Kbit, prescaler: 24
48Mhz, 500Kbit, prescaler: 6
8Mhz, 500Kbit, prescaler: 1

Bei hohen raten und geringem Takt funktioniert functioniert 13/2 nicht mehr

Fuer 10/1; prescaler=Clock/speed/12; (Clock/speed)%12 muss 0 sein
48Mhz, 2000Kbit, prescaler: 2

Fuer 6/1; prescaler=Clock/speed/8; (Clock/speed)%8 muss 0 sein
16Mhz, 2000Kbit, prescaler: 2

Specified: 1Mbit, 500kBit, 250kBit, 125kBit, 50kBit, 20kBit, 10kBit, 5kBit

enum {
e1MBit = 1,
e500KBit = 2,
e250KBit = 4,
e125KBit = 8,
e50KBit = 20,
e20KBit = 50,
e10KBit = 100,
e5KBit = 200,
}
Speed = (1000/enum)*1000

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